1. Field of the Invention
The invention relates to a method for fabricating MOS transistor, and more particularly, to a method of defining polysilicon slot before formation of epitaxial layer.
2. Description of the Prior Art
In the field of semiconductor fabrication, the use of polysilicon material is diverse. Having a strong resistance for heat, polysilicon materials are commonly used to fabricate gate electrodes for metal-oxide semiconductor transistors. The gate pattern fabricated by polysilicon materials is also used to form self-aligned source/drain regions as polysilicon readily blocks ions from entering the channel region.
As the dimension of semiconductor devices decreases, the fabrication of transistors also improves substantially for fabricating small size and high quality transistors. Conventional approach of fabricating the gate of metal-oxide semiconductor (MOS) transistors typically forms a polysilicon layer on a semiconductor substrate and a hard mask on the polysilicon layer before using two photo-etching processes (PEP) to pattern the polysilicon layer and the hard mask into a gate of the transistor. Preferably, the first photo-etching process is conducted to pattern the hard mask and the polysilicon layer into a plurality of rectangular polysilicon gate pattern as the second photo-etching process forms a polysilicon slot in each of the rectangular gate pattern for separating each gate pattern into two gates. Thereafter, elements including spacers are formed on the sidewall of the gate and lightly doped drains and epitaxial layer are formed in the semiconductor substrate adjacent to two sides of the spacer.
However, as the polysilicon slot is preferably formed before the formation of epitaxial layer, the etching ratio involved during the formation of the polysilicon slot typically affects the process thereafter. For instance, if the etching ratio of the second photo-etching process is low, the gate pattern would not be etched through completely to form the polysilicon slot and phenomenon such as polysilicon residue and line end bridge would result, whereas if the etching ratio of the second photo-etching process is high, the hard mask disposed on top of the polysilicon gate pattern would be consumed, which would further induce consumption of the spacer formed on the sidewall of the gate thereafter. As some of the spacer on the sidewall is consumed away, a portion of the gate is exposed and un-wanted epitaxial layer would be formed on the exposed portion of the gate.